The invention relates to analog-to-digital (A/D) converters of the kind taught as prior art in U.S. Pat. No. 4,198,622, which is assigned to the assignee of the present invention. Basically, such A/D converters employ a successive approximation register (SAR) to generate a digital word in a particular sequence of bit combinations that relate to the analog voltage. A digital-to-analog (D/A) converter is used to convert the digital word to a voltage which is also related to a reference voltage (V.sub.REF) applied to the D/A converter. The D/A converter is coupled to a comparator which is also fed the analog voltage to be evaluated. The comparator output is coupled to the SAR to establish its word bit sequence. U.S. Pat. No. 4,191,900, which is also assigned to the assignee of the present invention, details a precision plural input comparator suitable for A/D converter applications.
In operation, the SAR establishes the digital word one bit at a time. The most significant bit (MSB) is determined first, by comparing the analog input with V.sub.REF. If the input is greater than V.sub.REF /2, the MSB is a one. If smaller, the MSB is a zero. Then the next MSB is established by comparing the analog input inside the previously determined V.sub.REF /2 value. In other words, the next MSB is determined in terms of V.sub.REF /4. Next, the bit associated with V.sub.REF /8 is determined and so on until all bits are evalulated. This selection process is well known in the prior art.
In CMOS circuits, the comparator taught as prior art in U.S. Pat. No. 4,191,900 is employed because of its speed and sensitivity. While such a comparator operates in a switching mode and is a-c coupled, it responds to d-c inputs. However, since the coupling capacitors must be charged in the switching cycle, there is some input loading which presents itself as an input current, the value of which is related to the change in input d-c value during the switching interval.
My copending application Ser. No. 146,477, filed Sept. 28, 1978, shows a circuit for reducing the loading on the analog input circuit. Here a CMOS voltage follower is connected into the comparator input during the switching cycle. Thus, the input current is supplied by the voltage follower during the initial portion of the cycle. Then the follower is shorted out and the comparator connected directly to the analog input. Using this arrangement reduces input loading because the voltage follower will charge the capacitance to within one transistor threshold of its final value. Input loading will then be reduced to only a minor, less than one threshold, charging requirement.